Innovations rapidly occur in integrated circuit structures of memory systems and in the information storage capacity of, for example, each dynamic random access memory (RAM) in those systems. With such innovations, greater demands are made for improved memory system integrity and reliability.
Transient single bit errors in dynamic RAMs occasionally impair memory system integrity and reliability. Such errors often result in the dynamic corrupting of a single stored bit of information and require the use of complex and costly error detection and correction circuitry, as well as, many real time processor operations to correct the error before it causes performance failures. Another deficiency in such prior art arrangements is the absence of facilities to perform maintenance functions which allow the identification of dynamic RAMs prone to transient errors due to manufacturing or design defects.